Using built-in Manual Mode on N2/C4

This document introduces to add ModeLine parameters into a kernel image on N2/C4. You need to build a kernel to do this.
Refer to the link below for more information on how to build a kernel on the N2/C4.
How to build a kernel on N2, How to build a kernel on C4

Define display name

You will define a display name in “hdmi_parameters.c” as follow.

.name = "480x1280p60hz"

That is the display name and we will use the same name in the “config.ini”

Prepare modeline parameters

You have to determine HDMI parameters first. Copy this template to your google sheet and fill the green area.
https://docs.google.com/spreadsheets/d/1ZinXWeVa1h7nAAB0x5EGrKc0aJ45nwnsfvYC00a-rSc/edit#gid=635008158

After determining ModeLine information, please refer to the patch file and add the code.

enc_cfg_hw.c

Please refer to the “AMlogic registers” in the google sheet. Fill the green area in the sheet and then add the generated register values into the code.
You can also refer to the sample patch about the other register values.

hdmi_tx_hw.c

Please refer to the “AMLogic tvenc parameters” in the google sheet. Fill the green area in the sheet and then add the generated values into the code.
You can also refer to the sample patch about the other parameters.

hw_clk.c

--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -835,6 +835,9 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
        {{HDMI_480x800p60_4x3,
          HDMI_VIC_END},
                2560000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+       {{HDMI_480x1280p60_3x8,
+         HDMI_VIC_END},
+               4512000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
        {{HDMI_CUSTOMBUILT,
          HDMI_VIC_END},

{{group}, hpll_clk_out, od1, od2, od3, vid_pll_div, vid_clk_div, hdmi_tx_pixel_div, encp_div, enci_div}
You can add the clock group based on the basic rules. And we will focus on the “hpll_clk_out” and “od1/od2/od3”.

IF hpll_clk > 2.8GHz, 		
	od1 = 1, od2 = 1, od3 = 2, pll_div=DIV_5	
	hpll_out = 10 x pixel_clock (2 x 1 x 1 x 5 = 10)	
IF 2.8GHz > hpll_clk > 1.4GHz,		
	od1 = 2, od2 = 1, od3 = 2, pll_div=DIV_5	
	hpll_out = 20 x pixel_clock (2 x 1 x 2 x 5 = 20)	
IF 1.4GHz > hpll_clk > 700MHz, 		
	od1 = 4, od2 = 1, od3 = 2, pll_div=DIV_5 	
	hpll_out = 40 x pixel_clock (4 x 1 x 2 x 5 = 40)	
IF 700MHz > hpll_clk ,		
	od1 = 4, od2 = 2, od3 = 2, pll_div=DIV_5	
	hpll_out = 80 x pixel_clock (4 x 2 x 2 x 5 = 80)	

In the case of the 480×1280 monitor example, the hpll_out value is “4512000” because the hpll_clk is 56.4 MHz.
The other divider parameters have the following values.
od1 = 4, od2 = 2, od3 = 2, pll_div=DIV_5

https://github.com/hardkernel/linux/blob/odroidg12-4.9.y/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c#L1159-L1191

Build the kernel source and install them into your SD card.
How to build a kernel on N2, How to build a kernel on C4

If you are using an old Ubuntu image so you don't have the config.ini file in the partition, check “boot.ini”.

Set the "display_autodetect" to "false" in config.ini

display_autodetect=false

Set the "hdmimode" to "480x1280p60hz" in config.ini

We have set the display mode name to “480x1280p60hz” in the patch files. Add the name in “hdmimode”.

hdmimode=480x1280p60hz

After the reboot, you can verify with this command if it is applied well.
The mode name must match the name of the display name in the source code.

odroid@odroid:~$ cat /sys/class/display/mode
480x1280p60hz