Expansion Connectors


The XU3/XU4 provides one 30-pin dual row expansion header “CON10”.
The location and pinout of these connectors is illustrated below. All signals on expansion headers are 1.8V except PWRON signal.

Default Pin State GPIO & Export No Net Name Pin Number Pin Number Net Name GPIO & Export No Default Pin State
- - 5V0 1 2 GND - -
I XADC0AIN_0 ADC_0.AIN0 3 4 UART_0.CTSN GPA0.2 (#173) I(PUDN)
I(PUDN) GPA0.3 (#174) UART_0.RTSN 5 6 UART_0.RXD GPA0.0 (#171) I(PUDN)
I(PUDN) GPA2.7 (#192) SPI_1.MOISI 7 8 UART_0.TXD GPA0.1 (#172) I(PUDN)
I(PUDN) GPA2.6 (#191) SPI_1.MISO 9 10 SPI_1.CLK GPA2.4 (#189) I(PUDN)
I(PUDN) GPA2.5 (#190) SPI_1.CSN 11 12 PWRON Input Range (1.8V ~ 5V) I
I(PUDN) GPX1.5 (#21) XE.INT13 13 14 I2C_1.SCL GPB3.3 (#210) I(PUDN)
I(PUDN) GPX1.2 (#18) XE.INT10 15 16 I2C_1.SDA GPB3.2 (#209) I(PUDN)
I(PUDN) GPX1.6 (#22) XE.INT14 17 18 XE.INT11 GPX1.3 (#19) I(PUDN)
I(PUDN) GPX2.6 (#30) XE.INT22 19 20 XE.INT20 GPX2.4 (#28) I(PUDN)
I(PUDN) GPX2.5 (#29) XE.INT21 21 22 XE.INT23 GPX2.7 (#31) I(PUDN)
I XADC0AIN_3 ADC_0.AIN3 23 24 XE.INT17 GPX2.1 (#25) I(PUDN)
I(PUDN) GPX1.7 (#23) XE.INT15 25 26 XE.INT16 GPX2.0 (#24) I(PUDN)
I(PUDN) GPX3.1 (#33) XE.INT25 27 28 GND - -
- - VDD_IO(1.8V) 29 30 GND - -

CON11 is available only in XU4 not XU3.
All signals on expansion headers are 1.8V

Default Pin State GPIO & Export No Net Name Pin Number Pin Number Net Name GPIO & Export No Default Pin State
- - 5V0 1 2 GND - -
- - VDD_IO(1.8V) 3 4 I2C_5.SDA GPA2.2 (#187) I(PUDN)
I(PUDN) GPX3.2 (#34) XE.INT26 5 6 I2C_5.SCL GPA2.3 (#188) I(PUDN)
I(PUDN) GPZ.0 (#225) I2S_0.SCLK 7 8 GND - -
I(PUDN) GPZ.1 (#226) I2S_0.CDCLK 9 10 I2S_0.SDO GPZ.4 (#229) I(PUDN)
I(PUDN) GPZ.2 (#227) I2S_0.LRCK 11 12 I2S_0.SDI GPZ.3 (#228) I(PUDN)

GPIO Map for WiringPi Library (CON10 2 x 15)

Net Name GPIO & Export No WiringPi GPIO Header Pin Header Pin WiringPi GPIO GPIO & Export No Net Name
5V0 5V0 1 2 GND GND
ADC_0.AIN0 AIN0(1.8V Max) GPIO_25 3 4 GPIO_01 GPA0.2(#173) UART_0.RTSN
UART_0.CTSN GPA0.3(#174) GPIO_00 5 6 GPIO_16 GPA0.0(#171) UART_0.RXD
SPI_1.MOSI GPA2.7(#192) GPIO_12 7 8 GPIO_15 GPA0.1(#172) UART_0.TXD
SPI_1.MISO GPA2.6(#191) GPIO_13 9 10 GPIO_14 GPA2.4(#189) SPI_1.CLK
SPI_1.CSN GPA2.5(#190) GPIO_10 11 12 PWR_ON(INPUT) PWR_ON
XE.INT13 GPX1.5(#21) GPIO_02 13 14 GPIO_09 GPB3.3(#210) I2C_1.SCL
XE.INT10 GPX1.2(#18) GPIO_07 15 16 GPIO_08 GPB3.2(#209) I2C_1.SDA
XE.INT14 GPX1.6(#22) GPIO_03 17 18 GPIO_19 GPX1.3(#19) XE.INT11
XE.INT22 GPX2.6(#30) GPIO_22 19 20 GPIO_21 GPX2.4(#28) XE.INT20
XE.INT21 GPX2.5(#29) GPIO_26 21 22 GPIO_23 GPX2.7(#31) XE.INT23
ADC_0.AIN3 AIN3(1.8V Max) GPIO_29 23 24 GPIO_11 GPX2.1(#25) XE.INT17
XE.INT15 GPX1.7(#23) GPIO_05 25 26 GPIO_06 GPX2.0(#24) XE.INT16
XE.INT25 GPX3.1(#33) GPIO_27 27 28 GND GND
VDD_IO VDD_IO(1.8V) 29 30 GND GND

GPIO Map for WiringPi Library (Shifter-Shield 40 Pin)

GPIO WiringPi Name Mode Initial Level Header Pin Header Pin Initial Level Mode Name WiringPi GPIO
3.3V 1 2 5v
209 8 I2C1.SDA ALT1 1 3 4 5v
210 9 I2C1.SCL ALT1 1 5 6 0v
18 7 GPIO. 18 IN 1 7 8 1 ALT1 UART0.TX 15 172
0v 9 10 1 ALT1 UART0.RX 16 171
174 0 GPIO.174 ALT1 1 11 12 1 ALT1 GPIO.173 1 173
21 2 GPIO. 21 IN 1 13 14 0v
22 3 GPIO. 22 IN 1 15 16 1 IN GPIO. 19 4 19
3.3v 17 18 1 IN GPIO. 23 5 23
192 12 MOSI ALT1 1 19 20 0v
191 13 MISO ALT1 1 21 22 1 IN GPIO. 24 6 24
189 SCLK ALT1 0 23 24 1 OUT CE0 10 190
0v 25 26 1 OUT GPIO. 25 11 25
187 30 I2C5.SDA ALT2 1 27 28 1 ALT2 I2C_5.SCL 31 188
28 21 GPIO. 28 IN 1 29 30 0v
30 22 GPIO. 30 IN 1 31 32 1 IN GPIO. 29 26 29
31 23 GPIO. 31 IN 1 33 34 0v
24 POWER ON 35 36 1 IN GPIO. 33 27 33
25 AIN.0 37 38 1v8 28
0v 39 40 AIN.3 29

The “gpio readall” shows the pin-map of 40-pin-Shifter-Shield not 30-Pin-header.

PCB Layout for pin map